Abstract :

In the present study the improved architecture of Inverse Fast Fourier Transform (FFT) is developed and presented. The number of arithmetic operation is more in the normal working of conventional Inverse Fast Fourier Transform. An enhanced pruning algorithm is utilized to reduce the number of arithmetic operations in the FFT architecture. The performance of the improved FFT architecture is estimated to find its suitability for the low power Wireless communication system. It was implemented in 8-point FFT architecture using decimation in frequency algorithm using hardware description language. It is implemented in XC7z020clg484-1 from Zynq-7000 family with a frequency of 220MHz. It is found that the improved FFT architecture reduces maximum of 40% of the arithmetic operations, which reduces the power consumption by maximum of 10%. Hence, the improved FFT architecture could be used in the signal processing units in wireless applications.